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A-V EZ-Extender Hardware Reference
Table 2-8. Setting Direction of PPI0_SYNC2 (JP6.2/4/6)
Jumper Location
JP6.2/4
JP6.4/6
Uninstalled
PPI0_SYNC2 Direction
Controlled by flag pin
Input to processor
Output from processor
I 2 S Enable Jumper (JP7.1/2)
When the JP7.1/2 jumper is installed, the SPORT signals are routed for
I 2 S SPORT communication protocol mode. To accomplish this, the
receive and transmit clocks of the processor are driven by the output clock
of the AD1836A. The same is done for the frame sync signals.
SPORT Data Connection Jumpers (JP7.3/4, JP7.5/6)
The JP7.3/4 and JP7.5/6 jumpers connect data output pins ( ASDATA1 and
ASDATA2 ) of the audio codec to the primary and secondary SPORT data
input pins of the processor. The audio codec is driving these pins—with
the help of the JP7.3/4 and JP7.5/6 jumpers, the processor’s pins can be
reused when the audio codec is disabled.
VID_OUT Bus SYNC Source Select Jumpers
(JP8.1/3/5, JP8.2/4/6)
The source of the PPI frame sync signals depends on the PPI port driving
the VID_OUT bus. When using PPI0 , place the jumpers at JP8.1/3 and
JP8.2/4 . When using PPI1 , place the jumpers at JP8.3/5 and JP8.4/6 .
VID_OUT Bus SYNC Enable Jumper (JP8.7/8)
To enable the VID_OUT frame sync signals, install the JP8.7/8 jumper.
Blackfin A-V EZ-Extender Manual
2-13
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